1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly relates to a semiconductor device having a write leveling mode for measuring a skew between a clock signal and a data strobe signal. The present invention also relates to a module including this semiconductor device and to a data processing system.
2. Description of Related Art
Transmission and reception of read data and write data between a semiconductor memory device such as a DRAM (Dynamic Random Access Memory) and a memory controller may be performed synchronously with a data strobe signal. For example, in a write operation, a memory controller supplies a data strobe signal and write data to a semiconductor memory device, and the semiconductor memory device fetches the write data synchronously with the data strobe signal.
However, the write data fetched by the semiconductor memory device is transferred to a memory cell array synchronously with a clock signal, which is different from the data strobe signal. Therefore, when a skew exists between the data strobe signal and the clock signal, a write operation cannot be performed correctly. To solve this problem, semiconductor memory devices often include a write leveling mode for measuring the skew between a clock signal and a data strobe signal (see JEDEC STANDARD, DDR3 SDRAM Specification, JESD79-3B (Revision of JESD79-3A, September 2007), April 2008, JEDEC SOLID STATE TECHNOLOGY ASSOCIATION <URL:http://www.jedec.org/download/search/JESD79-3B.pdf>).
Note that in the present application, the disclosure of the non-patent literature mentioned above is incorporated herein by reference.
Upon entering a write leveling mode, a semiconductor memory device samples a clock signal at a timing of a rising edge of a data strobe signal supplied from a memory controller, and outputs the sampled clock signal from a data terminal. With this configuration, the memory controller can acquire an amount of skew between the data strobe signal and the clock signal. Consequently, the memory controller can adjust an output timing of the data strobe signal by taking the amount into consideration.
Because the write leveling operation mentioned above is an operation of measuring a skew between a data strobe signal and a clock signal in a write operation, it is preferable to perform the operation in the same condition as that of an actual write operation as much as possible.
In an actual write operation, write data and a data strobe signal are input after a lapse of predetermined latency since a write command is issued. Further, when an ODT (On Die Termination) signal is input from the memory controller, a terminating resistance circuit connected to the data strobe terminal is activated after a lapse of predetermined latency. With this configuration, the data strobe terminal itself functions as a terminating resistance circuit, thereby preventing deterioration of signal quality due to a reflection of a data strobe signal.
In a write leveling mode, it is not necessary to input a write command and write data. However, an ODT signal is input to obtain the same condition as that of the actual write operation. Accordingly, in the write leveling mode, the terminating resistance circuit is activated after a lapse of predetermined latency since the ODT signal is input.
However, when the ODT signal has predetermined latency in the write leveling mode, it is necessary to wait for a lapse of the predetermined latency (ODT latency) until the terminating resistance circuit is activated, even there is no need to input a write command and write data. Consequently, the write leveling operation takes time disadvantageously.
While this problem is not so critical when a system is started or a module is reset, it becomes critical when write leveling is periodically performed in an operation after the system is started, because it leads to drop of system performance. To solve this problem, there is considered a method in which, when the system enters a write leveling mode, the terminating resistance circuit is activated constantly. However, this method leads to increase of power consumption.